Research and Development Cell
To create an environment for technology innovations and being recognized as one of the leading research centers in India.
1. Establish an atmosphere for faculty to engage in cutting edge research by providing required infrastructure and necessary financial assistance.
2. Provide students a platform to indulge in research and development through technology innovation.
3. Keep students up to date with latest technology inventions in their field of study through seminars and workshops.
4. Equip students to solve social relevant challenges through technology innovation.
Our faculties are currently pursuing their PhD’s in the following domains.
Name: Mrs. K. UdaySree
Department: Mechanical Engineering
Research Topic: Vibration based diagnostics for analysis of combustion
properties and noise emissions of IC engines. The main objective of this work is to study the reconstruction of the cylinder pressure from Vibration measurements for diagnosis purposes of IC engines. The final goal is to deliver a basic framework for an engineering method to perform the reconstruction of the cylinder pressure in similar engines of the same brand. The investigation is also extend to use of the reconstructed pressure for detecting start of the combustion process (SOC) for calculation of the beat release rate (BRR) and for prediction of the noise and exhaust emission.
Name: Mr. Syed Khamruddin
Department: Electrical and Electronics Engineering
Research Topic: Sensor less control of Induction motor using luenberger observer with fuzzy logic.The control and estimation of ac drives are more complex than those of dc drives,and this complexity increases if high performances are demanded. The main reasons of this complexity are the need of variable frequency, harmonically optimum converter power supplies and machine parameter variations. This research focuses on the sensor less control technique for speed estimation of Induction motor drive using the Luenberger Observer method. Variable frequency power supplies will be considered with voltage fed converters as they are popularly used in the industrial applications. In this scheme intelligent controls are provided using fuzzy logic.
Name: Mr. M. P. Mallesh
Department: Humanities and Sciences
Research Topic: MHD Nanofluid flow and heat transfer past a vertical oscillating plate with thermal radiation, viscous dissipation heat generation Numerical Study A mathematical model is depicted in the unsteady magneto hydrodynamic (MHD) nanofluid flow and heat transfer from a vertically oscillating plate in its own plane in the presence of thermal radiation, viscous dissipation and heat generation. A range of nanofluids containing nanoparticles Al2O3, Cu, Tio2 and Ag with nanoparticle volume fraction range less than or equal to 0.04 are considered. The Tiwari-Das nanofluid model is employed. The governing unsteady, coupled, non-linear partial differential equations are transformed into a system of nonlinear ordinary differential equations, with appropriate intial and boundary conditions. A robust Galerkin finite element numerical solution is developed. The obtained results are bench marked with previously published work for special cases of the problem in order to access the accuracy of the numerical method and found to be in excellent agreement. This study is relevant to high temperature, magnetic nanomaterial’s processing, thermal flow processing in the chemical engineering coating operations, solar energy collector system, and so on.
Name: Mrs. T. Sandhya
Department: Electronics and Communication Engineering
Research Topic: Design of sub-threshold circuit for ultralow power applications In the past, the major concerns of the VLSI designer were area, performance, cost and reliability. Power consideration was mostly of only secondary importance. In recent years, however, this has begun to change and increasingly, power is given comparable weight to area and speed considerations. Low power has emerged as a principal theme in today’s electronic industry. The need for low power has caused a major paradigm shift where power dissipation has become as important considerations as performance and area. Wide utilization of portable battery-operated devices in modern applications triggers a demand for ultra low power designs. Many circuit techniques have been successfully applied to reduce both dynamic and leakage components of power. Recently, subthreshold operation has gained a lot of attention due to ultra low- power consumption in applications requiring low to medium performance. It has also been shown that by optimizing the device structure, power consumption of digital sub threshold logic can be further minimized while improving its performance. Therefore subthreshold circuit design is very promising for future ultra low-energy sensor applications as well as high performance parallel processing.
Name: Mrs. S. Anusha
Department: Electronics and Communication Engineering
Research Topic: Design and implementation of reversible ALU in nanometer technology.
In low power circuit design, reversible computing has become one of the most efficient and prominent technique in recent years. Reversible logic is gaining significant consideration as the potential logic design style for implementation in modern nanotechnology. In this work, we propose reversible Arithmetic and Logic Unit (ALU) and we design, develop and implement and show its major implications on the Central Processing Unit (CPU).
This proposed ALU consists of eight operations, three arithmetic and five logical operations. The arithmetic operations include addition and subtraction, multiplication, division and the logical operations include NAND, AND, OR, NOT and XOR. All the modules are likely to be designed using the basic reversible gates. This work focuses on PFGA, HNG, DKG, PTR gates which are 4*4 reversible logic gates. The proposed design will be analysed and compared in terms of number of gates count, garbage output, quantum cost and propagation delay. Power, area and delay analysis of the various sub modules are compared with the traditional gates. The proposed ALU can be coded using Verilog; the design will be verified, simulated and synthesized using Xilinx ISE 12.2 software and using Cadence backend tool.